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february 2009 rev 8 1/12 12 tda7535 delta/sigma cascade 20 bit stereo dac features 20-bit resolution single ended output analog reconstruction third order chebyshev filter i 2 s input data format on chip pll system clock: 64 fs 2 output channels 0.9 v rms single ended output dynamic 3.3 v power supply reset sampling rate 36 khz to 48 khz description the tda7535 is a stereo, digital-to-analog converter designed for audio application, including digital interpolat ion filter, a third order multi-bit delta-sigma dac, a third order chebyshev's reconstruction filter and a differential to single ended output converter. this device is fabricated in highly advanced cmos, where high speed precision analog circuits are combined with high density logic circuits. the tda7535, according to standard audio converters, can accept any i 2 s data format. the tda7535 is available in so14 package. the total power consumption is less than 75 mw. tda7535 is suitable for a wide variety of applications where high performance are required. its low cost and single 3.3 v power supply make it ideal for several applications, such as cd players, mpeg aud io, midi applications, cd-rom drives, cd-interactive, digital radio applications and so on. an evaluation board is available to perform measurement and to make listening tests. so14 table 1. device summary order code package packing tda7535 so14 tube TDA7535013TR so14 tape and reel www.st.com obsolete product(s) - obsolete product(s)
contents tda7535 2/12 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 general interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 low voltage cmos interface dc electrical characteristics . . . . . . . . . . . . 5 2.7 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3i 2 s interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 obsolete product(s) - obsolete product(s)
tda7535 block diagram and pin description 3/12 1 block diagram and pin description figure 1. block diagram figure 2. pin connection (top view) table 2. pin function pin # pin name input/output power description 1n.c. -- 2 sdata i i2s digital data input 3 sck i i2s clock input 4n.c. -- 5 gnd_dig p digital ground 6 gnd_ana p analog ground 7 outsr o right channel single ended output 8 outsl o left channel single ended output 9 vcm p reference 1.65 v externally filtered 10 vdd_ana p analog 3.3 v supply 11 n.c. - - 12 vdd_dig p digital 3.3 v-supply 13 fsync i i2s left-right channel selector 14 resetn i reset (active low) fir1 fir2 alu s&h i 2 s i 2 s pll clkout digital input 20 fir3 20 4 ? modulator thermo decoder & randomizer 3rd chebyshev sc filter diff to single converter analog output f s 8f s 23 64f s d02au1417 n.c. sdata sck n.c. gnd_dig outsr gnd_ana outsl vdd_ana vcm n.c. vdd_dig fsync resetn 1 3 2 4 5 6 7 12 11 10 9 8 13 14 d01au1276a obsolete product(s) - obsolete product(s)
electrical specification tda7535 4/12 2 electrical specification 2.1 absolute maximum ratings warning: operation at or beyond these limit may result in permanent damage to the device. normal operation is not guaranteed at these extremes. 2.2 thermal data 2.3 recommended dc operating conditions table 3. absolute maximum ratings symbol parameter value unit v dd v cc power supplies digital analog -0.5 to +4.6 -0.5 to +4.6 v v v aio analog input and output voltage -0.5 to (v cc +0.5) v v dio digital input and output voltage -0.5 to (v dd +0.5) v v di5 digital input voltage (5 v tolerant) -0.5 to 6.5 v t j operating junction temperature range -40 to 125 c t stg storage temperature -55 to 150 c table 4. thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient (1) 1. in still air. 85 c/w table 5. recommended dc operating conditions symbol parameter test cond ition min. typ. max. unit v dd 3.3 v digital power supply voltage 3.15 3.3 3.45 v v cc 3.3 v analog power supply voltage 3.15 3.3 3.45 v obsolete product(s) - obsolete product(s)
tda7535 electrical specification 5/12 2.4 power consumption 2.5 general interface el ectrical characteristics 2.6 low voltage cmos interface dc electrical characteristics table 6. power consumption symbol parameter test condition min. typ. max. unit i dd total maximum current power supply @ 3.3 v and t j = 125 c 21.5 25 ma table 7. general interface electrical characteristics symbol parameter test condition min. typ. max. unit l il low level input current without pull-up device v i = 0 v (1) 1 a l ih high level input current without pull-up device v i = v dd (1) 1 a i latchup i/o latch-up current v < 0 v, v > v dd 200 ma v esd electrostatic protection leakage, 1 a (2) 2000 v 1. the leakage currents are generally very small, <1na. the val ue given here, 1ma, is the maximum that can occur after an electrostatic stress on the pin. 2. human body model. table 8. low voltage cmos interface dc electrical characteristics symbol parameter test condition min. typ. max. unit v il low level input voltage 0.2*v d d v v ih high level input voltage 0.8*v d d v v hyst schmitt trigger hysteresis 0.8 v obsolete product(s) - obsolete product(s)
electrical specification tda7535 6/12 2.7 dac electrical characteristics table 9. dac electrical characteristics v dd = 3.3 v; t amb = 25 c; input signal frequency = sinus wave generated by audio precision sys.2; input signal amplitude (see notes); noise integration bandwidth = 20 hz to 22 khz (a- weighted) parameter test condition min. typ. max. unit noise + distortion (1) 1. it is the ratio between the maximum input signal and t he integration of the in-band noise after deducing the power of signal fundamental. it depends on the input signal amplitude. in this case 0db means full scale digital, 1 khz frequency used. @0 db @-6 dbb @-40 db @-60 db 89 94 96 96 db db db db total harmonic distortion see note (2) 2. it is the ratio of the rms value of the signal fundament al component at 0 db (full scale digital) to the rms value of all of the harmonic components in the band. 70 (3) 3. by correlation to beuch resu lts. ate limits are 60 db. 94 db dynamic range see note (4) 4. measured using the snr at -60db input signal, wi th 60db added to compensate for small input signal. 84 (5) 5. by correlation to beuch resu lts. ate limits are 80 db. 96 db crosstalk see note (6) 6. left channel on with 0db/1khz input signal, right channel on with dc input signal. -95 db full scale output voltage v dd = 3.15 to 3.45 v full scale input 0.8 0.9 1.0 vrms input sampling rate 36 48 khz passband ripple 0.12 db stopband @ 3db @ 90db 44.1khz sampling rate 21.53 24.80 khz interchannel gain mismatch 0.05 0.1 db obsolete product(s) - obsolete product(s)
tda7535 i 2 s interface 7/12 3 i 2 s interface figure 3. i 2 s interface diagram figure 4. i 2 s timings fsync sdata sck 32 * sck 32 * sck 20 bits msb lsb 20 bits msb lsb left right t sck t sckpl t sds t lrw- t sckph t lrw+ t sdh valid fsync sdata sck valid t sckf t sckr table 10. timing characteristics timing description min. max. unit t sck clock cycle (1) 1/(64*fs) - 150ps rms 1/(64*fs) + 150ps rms ns t sckpl sck phase low 0.5*t sck - 1% 0.5*t sck +1% ns t sckph sck phase high 0.5*t sck - 1% 0.5*t sck +1% ns t lrw- fsync switching time window before sck falling edge (2) 0 0.125*t sck -10 ns t lrw+ fsync switching time window after sck falling edge (2)) 0 0.125*t sck -10 ns t sds sdata setup time 60 ns t sdh sdata hold time 30 ns obsolete product(s) - obsolete product(s)
i 2 s interface tda7535 8/12 figure 5. power up and reset sequence figure 6. frequency response t sckr sck rise time 22 ns t sckf sck fall time 20 ns 1. sck clock defines the fs, being the sample ra te. this input clock needs a jitter below ~212ps rms . 2. fsync switches inside the time window as specified w.r.t. to falling edge of sck. table 10. timing characteristics (continued) timing description min. max. unit t res t res min 50ms v dd reset d02au141 8 obsolete product(s) - obsolete product(s)
tda7535 application circuit 9/12 4 application circuit figure 7. application circuit 10 h bead inductor sdata 7 tp1 tp7 j4 bnc j3 bnc tp8 2 outsr sck tp2 3 fsync i 2 s tp3 13 gnd_dig 5 gnd_ana vcm 6 9 8 tp5 +3.3vana +3.3 vdig p r2 10k 100nf(*) 100nf(*) c15 47 f 10v (*) c7 10 f 10v 10 f 10 f sw1 c16 100nf (*) tp6 outsl 10 vdd_ana 12 vdd_dig resetn outsr outsl 14 d02au1419b u4 (*) as close as possible to the pin obsolete product(s) - obsolete product(s)
package information tda7535 10/12 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 8. so14 mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.30 0.004 0.012 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.01 d (1) 8.55 8.75 0.337 0.344 e 3.80 4.0 0.150 0.157 e 1.27 0.050 h 5.8 6.20 0.228 0.244 h 0.25 0.50 0.01 0.02 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) ?d? dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so14 0016019 d obsolete product(s) - obsolete product(s)
tda7535 revision history 11/12 6 revision history table 11. document revision history date revision changes 13-dec- 2003 5 initial release. 21-dec- 2005 6 update electrical characteristics. add revision history table. 03-feb-2006 7 updated max. value of t sckr and t sck t parameter on page 5/9. 06-feb-2009 8 document reformatted. updated section 5: package information on page 10 . obsolete product(s) - obsolete product(s)
tda7535 12/12 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com obsolete product(s) - obsolete product(s)

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